The present invention relates, generally, to analog to digital converters. More particularly, the present invention relates to an improved apparatus and method for gain calibration of over-sampled analog to digital converters.
A popular technique for implementing analog-to-digital converters includes the use of delta-sigma modulation wherein an analog voltage is input to a delta-sigma modulator. Such modulators produce noise, e.g., quantization and thermal noise, which is usually then reduced by a subsequent digital filter. The digital filter generally uses decimation in the filtering process, with the result that the digital data is output at a much slower rate than the output rate of the modulator, e.g., by converting from the sampling rate of the signal to a lower rate. This filtering process is generally operable to remove large amounts of noise at the cost of reducing the bandwidth of the analog-to-digital converter. Taking more than one sample per digital filter data output allows the analog-to-digital converter to average the samples, and thus improving accuracy at the expense of speed.
It is sometimes desirable to include amplification capabilities in an analog-to-digital converter, such as in a programmable gain amplifier. Without amplification, i.e., at unity gain, the full scale input signal typically equals the reference signal. With amplification, e.g., with a gain greater than one, the full scale input signal is a fraction of the reference signal. By scaling the voltage received at the input by increasing the gain, higher precision can be obtained.
The gain can be increased in various manners, for example as set forth more fully in U.S. Pat. No. 6,037,887, issued on Mar. 14, 2000 and assigned to the assignee of this application. In addition, the various manners for increasing the gain can include the increasing of the size of the input capacitor of the input sampling circuit, e.g., adding additional capacitors in parallel to the existing input capacitor, and/or multi-sampling which allows the gain to be adjusted by varying the rate of transfer of charge from the input capacitor relative to the rate of the modulator. Although there are advantages to analog-to-digital converters having gain capabilities, as discussed below, gain error can also be introduced.
In an ideal analog-to-digital converter, for every level of analog signal, there would be the intended corresponding digital signal. However, in reality, system imperfections degrade the accuracy of the digital representation of the analog signal resulting in errors, including offset error and gain error. Offset error exists when a zero voltage input signal generates a non-zero digital signal. Gain error exists when a non-zero analog input voltage creates a digital word which is greater or less than the intended result. The process of adjusting the digital output to correct for these errors is called calibration.
Calibration techniques generally involve the process of determining the amount of offset error and storing a compensating value in an offset calibration
coefficient, and determining the amount of gain error and storing a compensating value in a gain calibration coefficient. Afterwards, these coefficients are used to adjust output to correct for the offset and gain errors. Several methods for determining offset and gain calibration coefficients have been developed.
For example, an analog-to-digital converter may be calibrated at unity gain even though the device operates with a gain greater than one during a non-calibration mode. Furthermore, in unity gain sampling applications involving a single input capacitor, generally the whole charge associated with the calibration voltage is sampled onto the input capacitor. However, there also exists prior art gain calibration techniques that divide up an input capacitor into smaller parallel capacitors, sample a partial or fractional portion of the charge associated with the calibration voltage, and do not sample at a gain of one.
For example, U.S. Pat. No. 5,745,060, issued Apr. 28, 1998 to McCartney et al., as illustrated with reference to FIG. 1, discloses a technique and circuit that divides the total capacitance of the input sampling section into fractional portions of the total capacitance, e.g., divides the input capacitor from a capacitance value of C to four capacitors having a capacitance value of C/4, Next, this circuit samples through all of the capacitor portions at the modulator clock rate taking one sample with each capacitor portion, wherein each sample represents a fractional portion of the sampled calibration voltage, i.e., the technique samples a portion of the full scale charge. As a result, the calibration technique of McCartney intersperses all the samples from all the capacitor portions and creates one amalgamation of analog samples (prior to the digital filter) that is converted into a single digital word representing the calibration voltage.
However, the McCartney technique requires a clocking signal to rotate through the input capacitors. This clocking signal can possibly interfere with the other clocks signals and create unwanted low-frequency tones that appear in the output. Also, the noise of the calibration result will be approximately the same as the normal mode results since only one conversion is used to calculate the calibration coefficients.
Therefore, a need exists for a method and apparatus that performs gain calibration in a cleaner, less complex configuration, and with capabilities to reduce the noise and increase the accuracy of the analog-to-digital converter.
The present invention addresses many of the shortcomings of the prior art. In accordance with various aspects of the present invention, a method and apparatus for performing gain calibration of an analog to digital converter is provided. In accordance with an exemplary embodiment, during a calibration mode, an input sampling circuit comprised of multiple branches can be configured to provide a calibration mode gain of one. The analog-to-digital converter selects one of the parallel capacitor input sampling branches and repetitively samples the whole charge associated with the calibration voltage signal. This sampling step is repeated for each input sampling branch that is used during normal operation mode. The results of the sampling of the branches may be suitably averaged to create a gain calibration coefficient that is representative of and accounts for sampling variations between the input branches. Moreover, the analog-to-digital converter calibration can be performed regardless of whether the normal mode gain is equal to or higher than one.
The averaging of the sampled input branches can be conducted in various manners. In accordance with an exemplary embodiment, the samples of data from each capacitor branch are fully processed by the digital filter prior to averaging the results. In accordance with another exemplary embodiment, the separate data from the capacitor branches are merged in the digital filter, thus decreasing the time it takes to calibrate the analog-to-digital converter. In this embodiment, averaging occurs without the need to wait for complete settling of the digital filter for each input branch.